1. Field of the Invention
This invention relates to bipolar-CMOS (BiCMOS) semiconductor devices. More particularly, this invention relates to an efficient method for fabricating N-wells with structures optimized for both PMOS field effect transistors (FETs) and NPN bipolar transistors in a BiCMOS device.
2. Description of the Related Art
Early BiCMOS integrated circuits (ICs) were designed with predominantly CMOS logic gates and a relatively small number of bipolar input/output (I/O) drivers whose sole function was to provide adequate drive currents for external interfaces. At that time, processes were optimized for CMOS FETs, even to the detriment of bipolar transistor performance. Optimization for CMOS FETs was reasonable because the small number of non-optimal bipolar I/O transistors did not significantly degrade the overall IC performance. Because of the speed and drive abilities of the bipolar transistors, early BiCMOS ICs offered an overall performance improvement over CMOS-only ICs.
In a typical early BiCMOS circuit, bipolar transistors were fabricated by piggybacking bipolar process steps on as many CMOS fabrication steps as possible, so as to minimize the total number of fabrication steps. FIG. 1 shows a cross-sectional view of an early BiCMOS structure 100 using a P-type substrate 102. The process which produced structure 100 differs from a conventional CMOS process only by including an additional masking step. This additional masking step selectively produces lightly doped P- regions, such as P- region 101, which serve as the bases of NPN bipolar transistors. N-type bipolar collector regions, such as collector region 103, are formed by the same process step as that used to form CMOS N-well 104. Contacts for CMOS source and drain regions (e.g. regions 105-108) are also formed in the same step as contacts to the emitter, collector and base regions (e.g. regions 110, 103 and 111) of the bipolar transistors. Finally, semi-recessed local oxidation of silicon (LOCOS), such as oxide layer 112, isolates both the CMOS FETs and bipolar transistors.
More recently, higher performance BiCMOS processes have been developed to improve bipolar performance in the resulting devices. However, optimizing both bipolar and CMOS transistors typically requires several additional process steps. Two such higher performance conventional processes are the standard buried-collector (SBC) BiCMOS process and the modified twin-well BiCMOS process. FIGS. 2 and 3 are cross-sectional views of structures fabricated under the SBC and the modified twin-well BiCMOS processes, respectively.
While the SBC process is simpler than the modified twin-well process, i.e., three additional masking steps versus four additional masking steps, performance of bipolar transistors fabricated under the SBC process is lower than corresponding transistors fabricated under a twin-well process for two reasons. First, the packing density (i.e. the spacing between collectors of two adjacent bipolar transistors) is limited by a need to avoid the punchthrough phenomenon, which can occur due to the lightly doped P-substrate. Although higher packing density can be achieved by increasing the doping level in to the P-substrate, increasing the doping level in the P-substrate increases the collector-to-substrate capacitance (C.sub.CS). Second, in the SBC process, an N-type epitaxial layer is used, which is counterdoped for N-well isolation, and for forming P-wells. Such counterdoping in the epitaxial layer results in both processing problems and mobility degradation in the NMOS transistors. For such reasons, the modified twin-well process is more widely used than the SBC process.
FIG. 4 shows a typical process flow under the modified twin-well BiCMOS process, illustrated with reference to conventional CMOS and bipolar processes. The arrows in FIG. 4 indicate when the modified twin-well BiCMOS process steps are performed relative to the corresponding conventional CMOS and bipolar process steps.
In the modified twin-well process, design trade-offs include balancing the characteristics of the epitaxial layer and well profiles. A bipolar transistor requires a minimum epitaxial thickness (t.sub.epi(min)), which is determined by the bipolar breakdown voltage (BV.sub.CEO), C.sub.CS, base-to-collector capacitance (C.sub.BC) and process controllability. If the epitaxial layer is too thick, both the drive-current capability and the cut-off frequency (f.sub.T) of a resulting bipolar transistor diminish, while the collector resistance (R.sub.C) of such a bipolar transistor increases, resulting in an overall drop in drive-current capability. The ability to control the thickness of an epitaxial layer is limited by the heat-anneal cycles required in the formations of the collector and P isolation regions.
However, in the modified twin-well process, the use of P-buried layers to isolate adjacent N-wells dictates that the epitaxial layer be at least thick enough to prevent excessive increases, due to upward diffusion of the P+ buried layers, in (i) the NMOS body-effect coefficient, due to high doping in the substrate, and (ii) the junction capacitance between the N+ source and drain regions and the P-well. Thus, under the modified twin-well process, to decouple the NMOS parameters from the P-buried layer parameters, the doping of the P-buried layers is kept low and the epitaxial layer is made sufficiently thick.
Since both NPN bipolar transistors and PMOS FETs are fabricated within N-wells, the N-well profile is designed to accommodate a number of factors. For example, to prevent the Kirk effect in the bipolar transistors, the portion of an N-well below the base and above the buried collector is preferably heavily doped. (The Kirk effect is the "base push-out" effect, which results in reduced current gain at higher collector currents.) At the same time, the N-well doping is also required to be light enough to provide adequate BV.sub.CEO and BV.sub.CES.
CMOS FETs have N-well requirements that are different from, and sometimes competing with, the N-well requirements of the bipolar transistors. The N-well requirements for FETs include optimized threshold voltage (V.sub.T), punchthrough voltage, source/drain junction capacitance, and body effect. Typically, a blanket P-implant provides the desired V.sub.T for PMOS FETs, using a doping level high enough to prevent punchthrough and yet low enough to minimize the source/drain capacitance and body effect.
FIGS. 5a-5d are cross-sectional views of a prior art BiCMOS structure during various stages of fabrication under a modified twin-well BiCMOS process. In FIGS. 5a-5d, the same N-well is used for both PMOS FETs and NPN bipolar transistors. In FIG. 5a, a wafer having a P-type substrate 510 has a thin pad oxide layer 511 formed on one surface, and a thicker overlying nitride layer 512 formed on top of the pad oxide layer 511.
A first photoresist mask 540 is used to define deep N-well regions. Using photoresist mask 540, nitride layer 512 is etched to expose the pad oxide 511 layer. Then, an N-type ion implant step, indicated by reference numeral 560, is performed using a suitable dopant such as phosphorus, to form an N region 521. As shown in FIG. 5b, photoresist mask 540 is then removed and a second photoresist mask, N+ buried layer mask 541, is used to define regions for implanting N+ buried layers. An etching step removes the exposed portions of nitride layer 512 to expose pad oxide layer 511. A suitable N-type dopant, such as arsenic, is used in an ion-implantation step, indicated by reference numeral 561, to form N+ region 520. During the steps shown in FIG. 5b, N region 521 diffuses deeper into the P substrate 510.
After photoresist 541 is removed, an anneal step and a LOCOS field oxide formation step are performed to form LOCOS oxide layer 513, which is used to isolate the active regions. Prior to forming the LOCOS field oxide, an optional channel stop implant can be provided, if desired. After LOCOS field oxide 513 is formed, the remaining portions of nitride layer 512 are removed. The anneal step repairs the crystal lattice damage resulting from the previous implant steps and also serves to drive N region 521 and N+ region 520 deeper into substrate 510. Using LOCOS field oxide layer 513 as a mask, a high dose blanket P-type implant step, represented by reference numeral 563, is performed to form P+ regions 550a and 550d, as shown in FIG. 5c.
Next, both LOCOS field oxide layer 513 and pad oxide layer 511 are removed. A P-type epitaxial layer (EPI) 560 is then grown over the entire surface of the wafer. During the formation of epitaxial layer, the implanted N-type and P-type dopants diffuse deeper into substrate 510, and also diffuse upward into the epitaxial layer 560 as indicated in FIG. 5d by regions 551a, 520a, 551d and 521a, respectively. At this point, P+ region 550a, N+ region 520 and N region 521 have become P+ buried region 550a, N+ buried region 520 and deep N-well 521, by virtue of their positions beneath the EPI layer 560. The extents of the downward and upward diffusions depend on the relative dopant densities of the adjoining regions at their respective interfaces. The final step to achieve the structure shown in FIG. 5d is the fabrication of an N-well 522 in the epitaxial layer by either a diffusion, or another N-type ion implantation and anneal step, using a third photoresist mask. Regions 523a and 523b of P-type epitaxial layer 560 isolate N-well 522 from other similarly created N-wells. Hence, in the prior art process described above, a total of three photoresist masks are needed to form N-well 522 and N+ buried layer 520, 520a.
Having completed the N-wells for the NPN bipolar transistors and PMOS FETs, conventional fabrication steps can then be used to form the collector, base, emitter and contacts for the bipolar transistors, and the source, gate, drain and contacts for the PMOS FETs.
The article "A High-Performance Quadruple Well, Quadruple Poly BiCMOS Process for Fast 16 Mb SRAMs" by J. D. Hayden et al., IEDM 92, pp. 819-822, discloses the use of different buried layers having different well implants to form four distinct well regions: NPN bipolar, PMOS, peripheral NMOS, and array. FIG. 6 is a schematic cross-sectional view of a structure fabricated by such a quadruple well, quadruple polysilicon BiCMOS process. The array buried layer is added to achieve a low soft-error rate. The N-wells and the collector regions are physically separated in order to meet CMOS punchthrough and bipolar breakdown requirements.
Although the more recent BiCMOS processes described above are improvements over the early BiCMOS process, all the above described prior art BiCMOS processes share a number of common characteristics. First, in each of these processes, PMOS FETs and NPN bipolar transistors share the same type of N-well structure. Second, the N+ buried layer below the N-wells (e.g. N+ buried layer 520 of FIG. 5d) is in electrical contact with the P+ buried layer below the P-well (e.g. P+ buried layer 550a), which is grounded via the P-type substrate. Third, an additional isolating deep N-well, necessitating an additional masking step, is required under a P-well whenever a special NMOS FET is needed, such as in a memory cell or in an electrostatic discharge protection device. Fourth, defining both the N+ buried layer and the P+ buried layer also requires an additional masking step. Generally, the P+ buried layer is either implanted in a blanket fashion or is self-aligned to the N+ buried layer.
As a result, BiCMOS ICs fabricated using the above described prior art processes have at least two disadvantages. First, because a thin epitaxial layer is used to achieve faster bipolar transistors, PMOS FETs suffer from high P+/N-well capacitance. Second, because the P+ buried layer and the N+ buried layers are electrically connected, the bipolar transistors suffer from high collector-to-substrate capacitance (C.sub.cs).
Thus, the prior art fails to provide a single type of N-well structure which is optimized for both FETs and bipolar transistors. Accordingly, there is a need for fabricating N-wells or P-wells with differing parameters and hence characteristics so as to better optimize both bipolar transistors and FETs. Further, such process should preferably be achieved without further increasing the number of masking steps.